1. Field of the Invention
The present invention relates to manufacturing small dimension features of objects, such as integrated circuits, using photolithographic masks. More particularly, the present invention relates to the application of phase shift masking to complex layouts for integrated circuits and similar objects.
2. Description of Related Art
Phase shift masking, as described in U.S. Pat. No. 5,858,580, has been applied to create small dimension features in integrated circuits. Typically the features have been limited to selected elements of the design, which have a small, critical dimension. Although manufacturing of small dimension features in integrated circuits has resulted in improved speed and performance, it is desirable to apply phase shift masking more extensively in the manufacturing of such devices. However, the extension of phase shift masking to more complex designs results in a large increase in the complexity of the mask layout problem. For example, when laying out phase shift areas on dense designs, phase conflicts will occur. One type of phase conflict is a location in the layout at which two phase shift regions having the same phase are laid out in proximity to a feature to be exposed by the masks, such as by overlapping of the phase shift regions intended for implementation of adjacent lines in the exposure pattern. If the phase shift regions have the same phase, then they do not result in the optical interference necessary to create the desired effect. Thus, it is necessary to prevent inadvertent layout of phase shift regions in phase conflict.
Another problem with laying out complex designs which rely on small dimension features, arises because of isolated exposed spaces which may have narrow dimension between unexposed regions or lines.
Because of these and other complexities, implementation of a phase shift masking technology for complex designs will require improvements in the approach to the design of phase shift masks, and new phase shift layout techniques.
The present invention provides techniques for extending the use of phase shift techniques to implementation of masks for complex layouts in the layers of integrated circuits, beyond selected critical dimension features such as transistor gates to which such structures have been limited in the past, including xe2x80x9cdouble-Txe2x80x9d features. The invention provides a method that includes identifying features for which phase shifting can be applied, automatically mapping the phase shifting regions for implementation of such features, resolving phase conflicts which might occur according to a given design rule, and applying sub-resolution assist features within phase shift regions. The present invention is particularly suited to opaque field phase shift masks which are designed for use in combination with binary masks defining interconnect structures and other types of structures that are not defined using phase shifting, necessary for completion of the layout of the layer.
Various aspects of the invention include computer implemented methods for definition of mask layouts for corresponding complex layouts in the layers of integrated circuits to be made using such masks, methods for manufacturing masks having such mask layouts, methods for manufacturing integrated circuits having improved small dimension features implemented using the novel masks, and improved integrated circuits having the improved small dimension features.
The invention includes a method for producing photolithographic masks, and layout files for such photolithographic masks, which comprises identifying features in a pattern to be exposed having a dimension less than a particular feature size, and laying out phase shift regions using a layout rule for the identified features to produce a phase shift mask having phase shift areas. The particular feature size according to the invention need not be the critical dimension for the smallest features to be implemented. Rather, in the layout of an entire complex pattern, any feature which is suitable for implementation using phase shifting can be identified according to the present invention.
In one embodiment, the process of identifying features suitable for implementation using phase shifting includes reading a layout file which identifies features of the complex pattern to be exposed.
In one preferred embodiment, the phase shift mask includes an opaque field, and the phase shift regions include a plurality of transparent regions having a first phase within the opaque field, and a plurality of complementary transparent regions having a second phase 180 degrees out of phase with respect to the first phase, within the opaque field. The opaque field leaves unexposed lines formed by the phase shift regions unconnected to other structures. A complementary mask is laid out for use is conjunction with the opaque field phase shift mask to form interconnect structures in the region blocked by the opaque field, so the features formed using the phase shift mask are integrated with larger dimension features. In one embodiment, the complementary mask is a binary mask, without phase shifting features.
As a result of the layout rule, regions in the phase shift mask may result in phase conflicts. Thus, the invention also includes applying an adjustment to one or more of the phase shift regions in the phase shift mask to correct for phase conflicts. The adjustment in one preferred embodiment comprises dividing a phase shift region having a first phase into a first phase shift region having the first phase in a second phase shift region having the second phase. An opaque feature is added to the phase shift mask between the first and second phase shift regions. The complementary mask includes a corresponding opaque feature preventing exposure of the features to be exposed using the first and second phase shift regions in the phase shift mask, and includes a cut-out over the opaque feature separating the first and second phase shift regions to expose any feature resulting from the phase difference between the first and second phase shift regions. In one embodiment, the unique structure which results from the adjustment is laid out in the first instance to prevent phase conflicts in the layout, and so may not be considered an xe2x80x9cadjustmentxe2x80x9d to correct a phase conflict in the layout.
For example, phase conflicts can arise in the implementation of a pattern consisting of an intersection of an odd number of line segments. The odd number of line segments defines a plurality of corners at the intersection. In this case, phase shift regions are laid out adjacent the line segments on either side of the corner so they have the same phase, and preferably continuing around the corner in all of the plurality of corners, except one. In one excepted corner, a first phase shift region having the first phase is laid out adjacent the line segment on one side of the corner, and a second phase shift region having the second phase is laid out adjacent the line segment on the other side of the corner. An opaque feature is added between the first and second phase shift regions in the one corner. The complementary mask includes a corresponding opaque feature preventing exposure of the intersecting line segments left unexposed by the phase shift mask, and includes a cut-out over the opaque feature separating the first and second phase shift regions to expose any feature resulting from the phase difference in the one excepted corner between the first and second phase shift regions.
The selection of the one excepted corner having the cut-out feature in the structure that defines the intersection of an odd number of line segments is implemented in various embodiments according to design rules. In one design rule, the one excepted corner is the corner defining the largest angle less than 180 degrees. In another design rule, the one excepted corner is the corner which is the greatest distance away from an active region on the integrated circuit.
The present invention also provides for laying out structures referred to as xe2x80x9cdouble-Txe2x80x9d shapes, in which two line segments intersect at third line segment in locations that are close together. Often, the first and second line segments are parallel in the region of the intersection, and hence the xe2x80x9cdouble-Txe2x80x9d name, but they need not be parallel for the method to apply. Thus the present invention provides a method, that includes the steps of
(1) identifying features of a pattern for a layer to be formed using a photolithographic mask, the pattern consisting of a first line segment, a second line segment, and a third line segment, said first, second, and third line segments having respective first and second sides, and in which the first and second line segments intersect the third line segment on the first side of the third line segment at respective first and second intersections;
(2) laying out phase shift regions for the identified features to produce a phase shift mask, the phase shift mask having a single phase shift region between the first and second line segments, and complementary second and third phase shift regions extending adjacent to the first and second line segments on sides opposite to said single phase shift region, and a fourth phase shift region having the same phase as said single phase shift region on the second side of said third line; and
(3) laying out a complementary mask including an opaque feature preventing exposure of the intersections of first, second and third line segments defined using the phase shift mask.
In another embodiment of the xe2x80x9cdouble-Txe2x80x9d structure layout, two phase shift regions of the same phase are laid out between the first and second line segments. In another embodiment, an opaque feature between the two phase shift regions has a width, and yet another phase shift region is laid out adjacent the third line segment between the intersections abutting the opaque feature, having about the same width as the opaque feature, and having an opposite phase from said two phase shift regions.
In one embodiment, the pattern to be implemented includes exposed regions and unexposed regions. Exposed regions between unexposed regions (i.e., spaces between lines or other structures) having less than a particular feature size are identified for assist features. The particular feature size used for identification of exposed regions between unexposed regions may or may not be the same as the feature size used for selection of unexposed regions (i.e., lines) to be implemented using phase shift masking. According to this aspect of the invention, the process includes laying out phase shift regions in the phase shift mask to assist definition of edges of the unexposed regions between exposed regions.
According to another aspect of the invention, the process includes adding sub-resolution assist features inside a particular phase shift region in the phase shift mask. The sub-resolution features comprise in various embodiments features inside and not contacting the perimeter of the particular phase shift region. In other embodiments, the sub-resolution features result in division of a phase shift region having a first phase into first and second phase shift regions having the same phase. An opaque feature between the first and second phase shift regions acts as a sub-resolution feature to improve the shape of the resulting exposed and unexposed regions.
The sub-resolution features do not xe2x80x9cprintxe2x80x9d in the image being exposed, but affect the intensity profile at the wafer level, such as by improving contrast of the image and thereby improving process latitude, and changing the size of the printed image caused by the phase shift region in which the sub-resolution feature is laid out, such as for optical proximity correction OPC.
According to another aspect of the invention, the layout of phase shifting regions in an opaque field includes a step of simulating an intensity profile or other indication of the exposure pattern to be generated, and locating regions in the exposure pattern which are anomalous, such as by having higher intensity. Sub-resolution features are then added to the layout covering the anomalous regions in the exposure pattern.
The use of sub-resolution features within phase shift regions is applied uniquely for the formation of an array of closely spaced shapes, such as an array of capacitor plates used in dynamic random access memory designs.
An overall process for producing a layout file, or a photolithographic mask is provided that includes identifying features to be implemented using phase shifting, laying out phase shifting regions so as to prevent or minimize phase conflicts, applying sub-resolution assist features to the phase shift regions, and producing a layout file. Next, a complementary mask is laid out to complete definition of the exposure pattern so that features that are not implemented using the phase shift mask are interconnected with the features implemented by the phase shift mask.
A method for producing integrated circuits having improved small dimension structures includes applying a photo-sensitive material to a wafer, exposing the photosensitive material using the phase shift mask implemented as described above, exposing the photo-sensitive material using the complementary mask implemented as described above, and developing the photo-sensitive material. A next process step in the method for producing integrated circuits involves the removal of material underlying the photo-sensitive material according to the resulting pattern, or addition of material over the wafer according to the pattern resulting from the use of the phase shift and complementary masks. The resulting integrated circuit has improved, and more uniform line widths, and improved and more uniform spaces between structures on the device. In some embodiments, the resulting integrated circuit has intersecting lines defined with phase shift masks.
The invention results, therefore, in methods for producing mask layout files and photolithographic masks based on such layout files suitable for the implementation of complex designs extensively using phase shifting structures to define small dimension features. New manufacturing techniques and improved integrated circuits are therefore provided.
Other aspects and advantages of the present invention can be understood with review of the figures, the detailed description and the claims which follow.